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sl811hs embedded usb host/slave controlle r sl811hs cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document 38-08008 rev. *b revised june 13, 2005 1.0 features ? the first usb host/slave controller for embedded systems in the market with a standard microprocessor bus interface. ? supports both full-speed (12 mbps) and low-speed (1.5 mbps) usb transfer in both master and slave modes ? conforms to usb specification 1.1 for full- and low-speed ? operates as a single usb host or slave under software control ? automatic detection of eit her low or full-speed devices ? 8-bit bidirectional data, port i/o (dma supported in slave mode) ? on-chip sie and usb transceivers ? on-chip single root hub support ? 256-byte internal sram buffer ? ping-pong buffers for improved performance ? operates from 12- or 48-mhz crystal or oscillator (built-in dpll) ? 5v-tolerant interface ? suspend/resume, wake up, and low-power modes are supported ? auto-generation of sof and crc5/16 ? auto-address increment mode, saves memory read/write cycles ? development kit including source code drivers is available ? backward-compatible with sl11h, both pin and function- ality ? 3.3v power source, 0.35 micron cmos technology ? available in both a 28-pin plcc package (sl811hs) and a 48-pin tqfp package (SL811HST-AC). 2.0 introduction 2.1 block diagram the sl811hs is an embedded usb host/slave controller capable of communicating in either full-speed or low-speed. the sl811hs can interface to devices such as micropro- cessors, microcontrollers, dsps, or directly to a variety of buses such as isa, pcmcia, and others. the sl811hs usb host controller conforms to usb specification 1.1. the sl811hs usb host/slave controller incorporates usb serial interface functionality along with internal full/low-speed transceivers. the sl811hs supports and operates in usb full- speed mode at 12 mbps, or at low-speed 1.5 mbps mode. when in host mode, the sl811h s is the master and controls the usb bus and the devices that are connected to it. in peripheral mode, otherwise known as a slave device, the sl811hs can operate as a variety of full or low speed devices. the sl811hs data port and microprocessor interface provide an 8-bit data path i/o or dma bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as motorola or intel cpus and many others. the sl811hs has 256-byte s of internal ram, which is used for control registers and data buffer. the available package types offered are a 28-pin plcc (sl811hs) and a 48-pin tqfp package (SL811HST-AC). both packages operate at 3.3 vdc. the i/o interface logic is 5v-tolerant. x1 x2 d + d- intr nwr nrd ncs nrst d0-7 generator usb root hub xcvrs serial interface engine 256 byte ram buffers control registers interrupt clock & controller processor interface master/slave controller ndrq ndack dma interface figure 2-1. sl811hs usb host/slave controller functional block diagram
sl811hs document 38-08008 rev. *b page 2 of 32 2.2 data port, microprocessor interface the sl811hs microprocessor in terface provides an 8-bit bidirectional data path along wit h appropriate control lines to interface to external processors or controllers. programmed i/o or memory mapped i/o designs are supported through the 8-bit interface, chip select, read and write input strobes and a single address line, a0. access to memory and control register space is a simple two step process, requiring an address write with a0 = ?0,? followed by a register/memor y read or write cycle with address line a0 = ?1.? in addition, a dma bi-directional interface in slave mode is available with handshake signals such as ndrq, ndack, nwr, nrd, ncs and intrq. the sl811hs write or read operation terminates when either nwr or ncs goes inactive. for devices interfacing to the sl811hs that deactivate the chip select ncs before the write nwr, the data hold timing should be measured from the ncs and will be the same value as specified. thus, both intel ? - and motorola-type cpus can work easily with the sl811hs without any external glue logic requirements. 2.3 dma controller (slave mode only) in applications that require transfers of large amounts of data such as scanner interfaces, the sl811hs provides a dma in- terface. this interface supports dma read or write transfers to the sl811hs internal ram buffer through the microprocessor data bus via two control lines (ndrq - data request and ndack - data acknowledge) along with the nwr line and con- trols the data flow into the sl811hs. the sl811hs has a count register that allows progr ammable block sizes to be se- lected for dma transfer. the control signals, both ndrq and ndack, are designed to be compatible with standard dma interfaces. 2.4 interrupt controller the sl811hs interrupt controller provides a single output signal (intrq) that can be acti vated by a number of program- mable events that may occur as result of usb activity. control and status registers are provided to allow the user to select single or multiple events, which will generate an interrupt (assert intrq), and let the user view interrupt status. the interrupts can be cleared by writing to the appropriate register (the interrupt status register). 2.5 buffer memory the sl811hs contains 256 bytes of internal memory used for usb data buffers, control registers and status registers. when in master mode (host mode), the memory is defined where the first 16 bytes are registers and the remaining 240 bytes are used for usb data buffers. when in slave mode (peripheral mode), the first 64 bytes are us ed for the 4 endpoint control and status registers along with th e various other registers. this leaves 192 bytes of endpoint buffer space for usb data transfers. access to the registers and data memory is through the 8-bit external microprocessor data bus, in either indexed or direct addressing. indexed mode uses the auto address increment mode described in section 2.5.1 auto address increment mode , where direct addressing is used to read/write to an individual address. usb transactions are automat ically routed to the memory buffer that is configured for th at transfer. control registers are provided, so that pointers and block sizes in buffer memory can be determined and allocated. 2.5.1 auto address increment mode the sl811hs supports auto increment mode to reduce read and write memory cycles. in th is mode, the microcontroller needs to set up the address only once. whenever any subse- quent data is accessed, the internal address counter will ad- vance to the next address location. 2.5.1.1 auto address increment example if filling the data buffe r that is configured to be at address 10h you would do the following: 1. write 10h to sl811hs with a0 low. this sets the memory address that will be used for the next operation. 2. write the first data byte into address 10h by doing a write operation with a0 high. an example would be if you were doing a get descriptor, the first byte that would be sent to the device would be 80h (bmrequesttype) so you would write 80h to address 10h. 3. now the internal ram address pointer is set to 11h so by doing another write with a0 high, ram address location 11h will be written with the dat a. continuing with the get descriptor example a 06h would be written to address 11h for the brequest value. 4. step 3 would then be repeated until all of the required bytes have been written necessary for a transfer. if auto-incre- menting is not used you woul d write the address value each time before writing the data as shown in step 1. the advantage of auto addre ss increment mode is that it reduces the number of sl811hs memory read/write cycles required to move data to/from the device. for example, trans- ferring 64-bytes of data to/from sl811hs using auto increment mode, will reduce the number of cycles to 1 address write and 64 read/write data cycles, compared to 64 address writes and 64 data cycles for random access. 0x00 ? 0x0f control and status registers 0x10 ? 0xff usb data buffer 240 bytes 16 bytes 0x00 ? 0x39 control/status registers and endpoint control/status registers 0x40 ? 0xff usb data buffer 192 bytes 64 bytes host mode memory map peripheral mode memory map figure 2-2. memory map
sl811hs document 38-08008 rev. *b page 3 of 32 2.6 pll clock generator either a 12-mhz or a 48-mhz external crystal can be used with the sl811hs [1] . two pins, x1 and x2, are provided to connect a low-cost crystal circuit to the device as shown in figure 2-3 and figure 2-4 . if an external clock source is available in the application, it can be used instead of the crystal circuit by connecting the source directly to the x1 input pin. when a clock is used, the x2 pin is left unconnected. when the cm pin is tied to a logic 0 the internal pll is bypassed so the clock source must meet the timing require- ments specified by the usb specification. 2.6.1 typical crystal requirements the following are examples of ?typical requirements?. please note that these specifications are generally found as standard crystal values and are theref ore less expensive than custom values. if crystals are used in series circuits, load capacitance is not applicable. load capacitance of parallel circuits is a requirement. note that for 48-m hz third overtone crystals will require the cin/lin filter to guarantee 48-mhz operation. 2.7 usb transceiver the sl811hs has a built in transceiver that meets usb speci- fication 1.1. the transceiver is capable of transmitting and receiving serial data at usb full speed (12 mbits) and low speed (1.5 mbits). the driver portion of the transceiver is differ- ential while the receiver section is comprised of a differential receiver and two single-ended receivers. internally, the trans- ceiver interfaces to the serial interface engine (sie) logic. externally, the transceiver connects to the physical layer of the usb. 3.0 sl811hs registers operation and control of th e sl811hs is managed through internal registers. when opera ting in master/host mode, the first 16 address locations are de fined as register space. in slave/peripheral mode the first 64 bytes are defined as register space. the register definitions vary greatly between each mode of operation and are defined separately in this document (section 3.1 describes host register definitions while section 3.2 describes slave register definitions). access to the registers are through the microprocessor interface just like note: 1. cm (clock multiply) pin of the sl811hs should be tied to g nd when 48-mhz crystal circuit or 48-mhz clock source is used. cbk 0.01 f rs 100 x1 48 mhz, series, 20-pf load cout 22 pf rf 1m x2 cin 22 pf lin 2.2 h x1 figure 2-3. full-speed 48-mhz crystal circuit x1 12 mhz , series, 20-pf load rf 1m cin 22 pf cout 22 pf rs 100 x2 x1 figure 2-4. optional 12-mhz crystal circuit 12-mhz crystals: frequency tolerance: 100 ppm or better operating temperature range: 0 c to 70 c frequency: 12 mhz frequency drift over temperature: 50 ppm esr (series resistance): 60 ? load capacitance: 10 pf min. shunt capacitance: 7 pf max. drive level: 0.1?0.5 mw operating mode: fundamental 48-mhz crystals: frequency tolerance: 100 ppm or better operating temperature range: 0 c to 70 c frequency: 48 mhz frequency drift over temperature: 50 ppm esr (series resistance): 40 ? load capacitance: 10 pf min. shunt capacitance: 7 pf max. drive level: 0.1?0.5 mw operating mode: third overtone
sl811hs document 38-08008 rev. *b page 4 of 32 normal ram accesses (see section 5.6) and provide control and status information for usb transactions. any write to control register 0fh will enable the sl811hs full features bit. this is an internal bit of the sl811hs that enables additional features not supported by the sl11h. for sl11h hardware backward compatibility, this register should not be accessed. table 3-1. shows the memory map and register mapping of both the sl11h and sl811hs in master/host mode. the sl11h is shown for users upgrading to the sl811hs. 3.1 sl811hs master (host) mode registers the registers in the sl811hs are divided into two major groups. the first group is referred to as usb control registers. these registers enable and provide status for control of usb transactions and data flow. the second group of registers provides control and status for all other operations. 3.1.1 register values on power-up and reset the following registers initialize to zero on power-up and reset: ? usb-a/usb-b host control register [00h, 08h] bit 0 only ? control register 1 [05h] ? usb address register [07h] ? current data set/ hardware revision/sof counter low register [0eh] all other registers power-up and reset in an unknown state and should be initialized by firmware. 3.1.2 usb control registers communication and data flow on the usb bus uses the sl811hs? usb a-b control r egisters. the sl811hs can communicate with any usb device functions and any specific endpoints via the usb-a or usb-b register sets. the usb a-b host control registers can be used in an overlapped configuration to ma nage traffic on the usb bus. the usb host control register also provides a means to interrupt an external cpu or micro controller when one of the usb protocol transactions is completed. table 3-1 and table 3-2 show the two sets of u sb host control registers, the ?a? set and ?b? set. the two register sets allow for overlapped operation. when one set of parameters is being set up, the other can be transferring. on completion of a transfer to an endpoint, the next operation will be controlled by the other register set. note . on the sl11h, the usb-b set control registers are not used. the usb-b register set can be used only when sl811hs mode is enabled by initializing register 0fh. the sl811hs usb host control has two groups of five registers each, which map in the sl811hs memory space. these registers are defined in the following tables. 3.1.2.1 sl811hs host control registers table 3-1. sl811hs master (host) register summary register name sl11h and sl811hs sl11h (hex) address sl811hs (hex) address usb-a host control register 00h 00h usb-a host base address 01h 01h usb-a host base length 02h 02h usb-a host pid, device endpoint (write)/usb status (read) 03h 03h usb-a host device address (write)/transfer count (read) 04h 04h control register 1 05h 05h interrupt enable register 06h 06h reserved register reserved reserved usb-b host control register reserved 08h usb-b host base address reserved 09h usb-b host base length reserved 0ah usb-b host pid, device endpoint (write)/usb status (read) reserved 0bh usb-b host device address (write)/transfer count (read) reserved 0ch status register 0dh 0dh sof counter low (write)/hw revi- sion register (read) 0eh 0eh sof counter high and control regis- ter 2 reserved 0fh memory buffer 10h-ffh 10h-ffh table 3-2. sl811hs host control registers register name sl11h and sl811h sl11h (hex) address sl811hs (hex) address usb-a host control register 00h 00h usb-a host base address 01h 01h usb-a host base length 02h 02h usb-a host pid, device endpoint (write)/usb status (read) 03h 03h usb-a host device address (write)/transfer count (read) 04h 04h usb-b host control register reserved 08h usb-b host base address reserved 09h usb-b host base length reserved 0ah usb-b host pid, device endpoint (write)/usb status (read) reserved 0bh usb-b host device address (write)/transfer count (read) reserved 0ch
sl811hs document 38-08008 rev. *b page 5 of 32 3.1.2.2 usb-a/usb-b host control registers [address = 00h, 08h] once the other sl811hs cont rol registers are configured (registers 01h-04h or 09h-0ch) the host control register is programmed to initiate the usb transfer. this register will initiate the transfer when the enable and arm bit are set as described above. 3.1.2.3 usb-a/usb-b host base address [address = 01h, 09h] the usb-a/b base address is a pointer to the sl811hs memory buffer location for usb reads and writes. when transferring data out (host to device), the usb-a and usb-b host base a ddress registers can be set up prior to setting arm on the usb- a or usb-b host control register. when using a double buffer sche me the host base address could be set up with the first buffer being used for data0 data and the other for data1 data. table 3-3. usb-a/usb-b ho st control register definition [address 00h, 08h] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 preamble data toggle bit syncsof iso reserved direction enable arm bit position bit name function 7 preamble if bit = ?1? a preamble token is transmitted pr ior to transfer of low-speed packet. if bit = ?0,? preamble generation is disabled. ? the sl811hs automatically generates preamble packets when bit 7 is set. this bit is only used to send packets to a low-speed device through a hub. to communicate to a full speed device, this bit is set to zero. fo r example, when sl811hs communicates to a low-speed device via the hub: ? sl811hs sie should be set to operate at fu ll-speed, i.e., bit 5 of register 05h (control register 1) should be equal to ?0.? ? bit 6 of register 0fh (control register 2) should be set = ?0,? se t correct polarity of data+ and data? state for full speed. ? bit 7, preamble bit, should be set = ?1? in host control register. ? when sl811hs communicates directly to low-speed device: ? bit 5 of register 05h (control register 1) should be set = ?1.? ? bit 6 of register 0fh (contr ol register 2) should be set = ?1,? data+ and data? polarity for low speed. ? the state of bit 7 is ignored in this mode. 6 data toggle bit ?0? if data0, ?1? if data1 (only used for out tokens in host mode). 5 syncsof ?1? = synchronize with the sof transfer when operating in fs only. the sl811hs uses bit 5 to enable transfer of a data packet after a sof packet is transmitted. when bit 5 = 1, the next enabled packet will be sent after next sof. if bit 5 = 0 the next packet is sent immediately if the sie is free. if operating in low-speed, do not set this bit. 4 iso when set to ?1? allows isochronous mode for this packet. 3 reserved bit 3 is reserved for future usage. 2 direction when equal to ?1? transmit (out). when equal to ?0? receive (in). 1 enable if enable = ?1?, allows transfers to occur. if enable = ?0?, usb transactions are ignored. the enable bit is used in conjunction with the arm bit (bit 0 of this register) for usb transfers. 0 arm allows enabled transfers when arm = ?1.? cleared to ?0? when transfer is complete (when done interrupt is asserted). table 3-4. usb-a/usb-b host base address definition [address 01h, 09h] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hbadd7 hbadd6 hbadd5 hbadd4 hbadd3 hbadd2 hbadd1 hbadd0
sl811hs document 38-08008 rev. *b page 6 of 32 3.1.2.4 usb-a/usb-b host base length [address = 02h, 0ah] the usb a/b host base length register contains the maximum packet size to be transferred between the sl811hs and a slave usb peripheral. essentially, this designates the largest packet size that can be transferre d by the sl811hs. base length designates the size of data packet to be sent or received. for example, in full- speed bulk mode the maximum packet length is 64 bytes. in iso mode, the maximum packet length is 1023, si nce the sl811hs only has an 8-bit length; the maximum packet size for the iso mode using the sl811hs is 255 ? 16 bytes (register space). when the host base length register is set to zero, a zero-length packet will be transmitted. 3.1.2.5 usb-a/usb-b usb packet status (read) and host pid, device endpoint (write) [address = 03h, 0bh] this register has two modes dependent on whether it is read or written. when read, this register provides packet status and it contains information relative to the last packet that has been rece ived or transmitted. this register is not valid to be read u ntil after the done interrupt has occurred, which will cause the register to be updated. the register is defined as follows. when written, this register provides the pid and endpoint informa tion to the usb sie engine to be used in the next transaction. all sixteen endpoints can be addressed by the sl811hs. pid[3:0]: 4-bit pid field (see table below), ep[3:0]: 4-bit endpoint value in binary. table 3-5. usb-a / usb-b host base le ngth definition [address 02h, 0ah] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hbl7 hbl6 hbl5 hbl4 hbl3 hbl2 hbl1 hbl0 table 3-6. usb-a/usb-b usb packet status regi ster definition when read [address 03h, 0bh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stall nak overflow setup sequence time-out error ack bit position bit name function 7 stall slave device returned a stall. 6 nak slave device returned a nak. 5 overflow overflow condition - maximum length exceeded during receives. for underflow, see section 3.1.2.6. 4 setup this bit is not applicable for host operat ion since a setup packet is generated by the host. 3 sequence sequence bit. ?0? if data0, ?1? if data1. 2 time-out time-out occurred. a time-out is defined as 18-bit times without a device response (in full- speed). 1 error error detected in transmission. this includes crc5, crc16, and pid errors. 0 ack transmission acknowledge. table 3-7. usb-a / usb-b host pi d and device endpoint register when written [address 03h, 0bh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pid3 pid2 pid1 pid0 ep3 ep2 ep1 ep0 pid type d7-d4 setup 1101 (d hex) in 1001 (9 hex) out 0001 (1 hex) sof 0101 (5 hex) preamble 1100 (c hex) nak 1010 (a hex) stall 1110 (e hex) data0 0011 (3 hex) data1 1011 (b hex)
sl811hs document 38-08008 rev. *b page 7 of 32 3.1.2.6 usb-a/usb-b host transfer count register (read), usb address (write) [address = 04h, 0ch] this register has two different functions depend ing on if it is read or wr itten. when read, this regi ster contains the number o f bytes left over (from host base length value) after a packet is transferred. for example, if t he base length register was set t o 0x040 and an in token was sent to the peripheral device. if, after the transfer was complete, the value of the host transfer co unt was 0x10, the number of bytes actually transferred would be 0x30. this is can be thought of as an underflow indication. when written, this register will contain the usb devi ce address to which the host wishes to communicate da6-da0 device address, up to 127 devices can be addressed da7 reserved bit should be set zero. 3.1.3 sl811hs control registers the next set of registers are the control registers and control more of the overall operation of the chip instead of usb packet types of transfers. note in the following table the sl11h and sl 811h are differentiated mainly du e to the fact that register 0f h was not valid in the sl11h but is left here for users who are familiar with the sl11h. table 3-8. usb-a / usb-b ho st transfer count register when read [address 04h, 0ch] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 htc7 htc6 htc5 htc4 htc3 htc2 htc1 htc0 table 3-9. usb-a / usb-b usb addre ss when written [address 04h, 0ch] bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 0 da6 da5 da4 da3 da2 da1 da0 table 3-10. sl811hs control registers summary register name sl11h and sl811h sl11h (hex) address sl811hs (hex) address control register 1 05h 05h interrupt enable register 06h 06h reserved register 07h 07h status register 0dh 0dh sof counter low (write)/hw revision register (read) 0eh 0eh sof counter high and control register 2 reserved 0fh memory buffer 10h-ffh 10h-ffh
sl811hs document 38-08008 rev. *b page 8 of 32 3.1.3.1 control regist er 1 [address = 05h] the control register 1 enables/disables usb transfe r operation with control bits defined as follows. at power-up this register will be cleared to all zeros. low-power modes [bit 6 control register, address 05h] when bit-6 (suspend) is set to ?1,? the power of the transmit transceiver will be turned off, the internal ram will be in the suspend mode, and the internal clocks will be disabled. note: any activity on the usb bus (i.e., k-state, etc.) will resume normal operation. to resume normal operation from the cpu side, a data write cycle (i.e., a0 set high for a data write cycle) should be done. this is a special case and not a normal direct write where the address is first written and then the data. to resume normal operation from the cpu side you must do a data write cycle only. low-speed/full-speed modes [bit 5 control register 1, address 05h] the sl811hs is designed to communicate with either full- or low-speed devices. at power-up bit 5 will be low, i.e., for full- speed. there are two cases when communicating with a low- speed device. when a low-speed device is connected directly to the sl811hs, bit 5 of register 05h should be set to ?1? and bit 6 of register 0fh, polarity swap, needs to be set to ?1? in order to change the polarity of d+ and d?. when a low-speed device is connected via a hub to sl811hs, bit 5 of register 05h should be set to ?0? and bit 6 of register 0fh should be set to ?0? in order to keep the polarity of d+ and d? for full speed. in addition, make sure that bit 7 of usb-a/usb-b host control registers [00h, 08h] is set to ?1? for preamble generation. j-k programming states [bits 4 and 3 of control register 1, address 05h] the j-k force state control and usb engine reset bits can be used to generate usb reset condition. forcing k-state can be used for peripheral device remote wake-up, resume and other modes. these two bits are set to zero on power-up. usb reset sequence a typical reset sequence consists of the following: after a device is detected, writ e 08h to the control register (05h) to initiate the usb reset, then wait the usb reset time (root hub should be 50 ms), additionally some types of devices like a forced j-state, lastly set the control register (05h) back to 0h. after the reset is complete, the auto-sof generation should be enabled. sof packet generation the sl811hs automatically comp utes the frame number and crc5 by hardware. no crc or sof is required to be generated by external firmware for the sl811hs although it can be done by sending an sof pid in the host pid, device endpoint register. to enable sof generation, assuming host mode is configured: 1. set up the sof interval in registers 0x0f and 0x0e. 2. enable the sof hardware generat ion in this register by set- ting bit 0 = 1. 3. set the arm bit in the usb-a host control register. table 3-11. control register 1 [address 05h] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved suspend usb speed j-k state force usb engine reset reserved reserved sof ena/dis bit position bit name function 7 reserved 0 6 suspend ?1? enable, ?0? = disable. 5 usb speed ?0? set-up for fu ll speed, ?1? set-up low-speed. 4 j-k state force see the table below. 3 usb engine reset usb engine reset = ?1.? normal set ?0?. when a device is detected, the first thing that must be done is to send it a usb reset to force it into its default address of zero. the u sb 2.0 specification states that for a root hub a device must be reset for a minimum of 50ms. 2 reserved some existing firmware examples set bit 2 but it is not necessary. 1 reserved 0 0 sof ena/dis ?1? = enable auto hardware sof generation; ?0? = disable. in the sl811hs, bit 0 is used to enable hw sof auto-generation (bit 0 was not used in the sl11h). the generation of sofs is still occurring when set to 0, but sof tokens are not output to usb. (see ) table 3-12. control register 1 address 05h ? bits 3 and 4 bit 4 bit 3 function 0 0 normal operating mode 0 1 force usb reset, d+ and d? are set low (se0) 1 0 force j-state, d+ set high, d? set low [2] 1 1 force k-state, d? set high, d+ set low [3] notes: 2. force k-state for low speed. 3. force j-state for low speed.
sl811hs document 38-08008 rev. *b page 9 of 32 3.1.3.2 interrupt enable register [address = 06h] the sl811hs provides an interrupt request output, which can be activated for a number of conditions. the interrupt enable register allows the user to select conditions that will result in an interrupt being issued to an external cpu via the intrq pin. a separate interrupt status register reflects the reason for the interrupt. enabling or disabling these interrupts does not have an effect on whether or not the corresponding bit in the interrupt status register will be set or cleared, it only determines if the interrupt will be routed to the intrq pin. the interrupt status register is no rmally used in conjunction with the interrupt enable register and can be polled in order to determine the conditions that initiated the interrupt (see interrupt status register description). when a bit is set to ?1? the corresponding interrupt is enabled, so when the enabled interrupt occurs, the intrq pin will be asserted. the intrq pin is a level interrupt, meaning it will not be deasserted until all enabled interrupts are cleared. 3.1.3.3 usb address register, re served, address [address = 07h] this register is reserved for the device usb address in slav e operation. it should not be written by the user in host mode. 3.1.3.4 registers 08h- 0ch host-b registers registers 08h-0ch have the same definition as registers 00h-04h except they apply to host-b instead of host-a. 3.1.3.5 interrupt st atus register, address [address = 0dh] the interrupt status register is a read/write register provid ing interrupt status. interrupts can be cleared by writing to this register. to clear a specific interrupt, the register is written with corresponding bit set to ?1.? table 3-13. interrupt enable register [address 06h] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved device detect/resume inserted/ removed sof timer reserved reserved usb-b done usb-a done bit position bit name function 7 reserved 0 6 device detect/resume enable device detect/resume interrupt. when bit-6 of register 05h (control register 1) is equal to ?1,? bit 6 of this register enables the resume detect interrupt. other wise, this bit is used to enable device detection status as defined in the interrupt status register bit definitions. 5 inserted/removed enable slave insert/remove de tection - used to enable/disable the device inserted/removed interrupt. 4 sof timer 1 = enable interrupt fo r sof timer. this is typically at 1ms intervals although the timing is determined by the sof counter high/low registers. to utilize this bit function, bit 0 of regi ster 05h must be enabled and the sof counter registers 0ehand 0fh must be initialized. 3 reserved 0 2 reserved 0 1 usb-b done usb-b done interrupt. (see usb-a done interrupt). 0 usb-a done usb-a done interrupt. the done interrupt is triggered by one of the events that will be logged in the usb packet status register. the done interrupt will cause the packet status register to be updated. table 3-14. interrupt status register [address 0dh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d+ device detect/resume insert/remove sof timer reserved reserved usb-b usb-a bit position bit name function 7 d+ value of the data+ pin. bit 7 provides continuous usb data+ line st atus. once it has been determined that a device has been inserted as described below with bits 5 and 6, bit 7 can be used to detect if the inserted device is low-speed (0) or full-speed (1).
sl811hs document 38-08008 rev. *b page 10 of 32 3.1.3.6 current data set register/hardwar e revision/sof counter low [address = 0eh] this register has two modes: a read from this regi ster indicates the current sl811hs silicon revision. writing to this register will set up auto generation of sof to all connected peripherals. this counter is based on the 12-mhz c lock and is not dependent on the crystal frequency. to set up a 1-ms timer interval, the software must set up both sof counter regis ters to the proper values. example: to set up sof for 1-ms interval, sof counter register 0eh should be set to e0h. 3.1.3.7 sof counter high/control register 2 [address = 0fh] when read, this register will return the va lue of the sof counter divided by 64. the so ftware should use this register to deter mine the available bandwidth in the current frame before initiating any usb transfer. in this way, the user will be able to avoid ba bble conditions on the usb. for example, to dete rmine the available bandwidth left in a frame: maximum number of clock ticks in 1-ms time frame is 12000 (1 count per 12-m hz clock period, or appr oximately 84 ns.) the value read back in register 0fh is the (c ount 64) 84 ns = time remaining in cu rrent frame. usb bit time = one 12-mhz period . value of register 0fh available bit times left are between bbh 12000 bits to 11968 (187 64) bits bah 11968 bits to 11904 (186 64) bits note: any write to the 0fh register will clear the internal frame co unter. register 0fh must be wr itten at least once after power- up. the internal frame counter is increment ed after every sof timer tick. the internal frame counter is an 11-bit counter, whic h is used to track the frame number. the fram e number is incremented after each timer tick. its contents are transmitted to the s lave every millisecond in a sof packet. 6 device detect/resume device detect/resume interrupt. bit 6 is shared between device detection status and resume detection interrupt. when bit-6 of register 05h is set to one, this bit will be the resume detection interrupt bit. otherwise, this bit is used to indicate the presence of a device, ?1? = device ?not present? and ?0? = device ?present.? in this mode this bit should be checked along with bit 5 to determine whether a device has been inserted or removed. 5 insert/remove device in sert/remove detection. bit 5 is provided to support usb cable insertion/removal for the sl811hs in host mode. this bit is set when a transition from se0 to idle (device inserted) or from idle to se0 (device removed) occurs on the bus. 4 sof timer 1 = interrupt on sof timer. 3reserved 0 2reserved 0 1 usb-b usb-b done interrupt. (see description in interrupt enable register [address 06h]). 0 usb-a usb-a done interrupt. (see description in interrupt enable register [address 06h]). table 3-15. hardware revi sion when read [address 0eh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hardware revision reserved bit position bit name function 7-4 hardware revision sl11h read = 0h, sl811hs rev1.2 read = 1h, sl811hs rev1.5 read = 2. 3-2 reserved read will be zero. 1-0 reserved reserved for slave. table 3-16. sof counter low addr ess when written [address 0eh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sof7 sof6 sof5 sof4 sof3 sof2 sof1 sof0 bit position bit name function
sl811hs document 38-08008 rev. *b page 11 of 32 when writing to this register the bits definition are defined as follows. note: any write to control register 0fh will enable the sl811hs full features bit. this is an internal bit of the sl811hs which enables additional features not supported by the sl11h. for sl11h hardware backward compatibility, this register should not be accessed. the usb-b register set can be used when sl811hs full feature bit is enabled. example . to set up host to generate 1-ms sof time: the register 0fh contains the upper 6 bits of the sof timer. register 0eh contains the lower 8 bits of the sof timer. the timer is based on an internal 12-mhz clock and uses a counter, which counts down to zero from an initial value. to set the timer for 1 ms time, the register 0eh should be loaded with value e0h and register 0fh (bits 0?5) should be loaded with 2eh. to start the timer, bit 0 of register 05h (control register 1) should be set to ?1?, which enables hardware sof generation. to load both high and low registers wit h the proper values the user must follow this sequence: 1. write e0h to register 0eh. this sets the lower byte of the sof counter 2. write aeh to register 0fh, aeh will configure the part for full-speed (no change of polarit y) host with bits 5?0 = 2eh for upper portion of sof counter. 3. enable bit 0 in register 0 5h. this enables hardware gener- ation of sof. 4. set the arm bit at address 00h. this starts the sof gen- eration. table 3-17. sof high counter when read [address 0fh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c13 c12 c11 c10 c9 c8 c7 c6 table 3-18. control register 2 when written [address 0fh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sl811hs master/slave selection sl811hs d+/d? data polarity swap sof high counter register bit position bit name function 7 sl811hs master/slave selection master = 1, slave = 0. 6 sl811hs d+/d? data polarity swap ?1? = change polarity (low-speed) ?0? = no change of polarity (full-speed). 5-0 sof high counter register write a value or read it back to sof high counter register.
sl811hs document 38-08008 rev. *b page 12 of 32 3.2 sl811hs slave mode registers when in slave mode, the registers in the sl811hs are divided into two major groups. the first group contains endpoint reg- isters that manage usb control transactions and data flow. the second group contains the usb registers that provide the control and status information for all other operations. 3.2.1 endpoint registers communication and data flow on usb is implemented using endpoints. these uniquely identifiable entities are the terminals of communication flow between a usb host and usb devices. each usb device is composed of a collection of independently operating endpoints. each endpoint has a unique identifier, which is the endpoint number. for more information, see usb specification 1.1 section 5.3.1. the sl811hs supports 4 endpoints numbered 0?3. endpoint 0 is the default pipe and is used to initialize and generically manipulate the device to configure the logical device as the default control pipe. it also provides access to the device's configuration information, allo ws usb status and control access, and supports control transfers. endpoints 1?3 support bulk, isochronous, and interrupt transfers. endpoint 3 is suppor ted by dma. each endpoint has two sets of registers?the 'a' set and the 'b' set. this allows overlapped operation where one set of parameters is being set up and the other is transferring. upon completion of a transfer to an endpoint, the 'next data set' bit indicates whether set 'a' or 'set 'b' will be used next. the 'armed' bit of the next data set will indicate whether the sl811hs is ready for the next transfer without interruption. 3.2.2 endpoints 0?3 register addresses each endpoint set has a group of five registers that are mapped within the sl811hs memory. the register sets have address assignments as shown in the following table. for each endpoint set (starting at address index = 0), the registers are mapped as shown in the following table: table 3-19. sl811hs slave/periph eral mode register summary register name endpoint specific register addresses ep 0 ? a ep 0 - b ep 1 ? a ep 1 - b ep 2 - a ep 2 - b ep 3 - a ep 3 - b ep control register 00h 08h 10h 18h 20h 28h 30h 0x38 ep base address register 01h 09h 11h 19h 21h 29h 31h 0x39 ep base length register 02h 0ah 12h 1ah 22h 2ah 0x32 0x3a ep packet status register 03h 0bh 13h 1bh 23h 2bh 0x33 0x3b ep transfer count register 04h 0ch 14h 1ch 24h 2ch 0x34 0x3c register name miscellaneous register addresses control register 1 05h interrupt status register 0dh interrupt enable register 06h current data set register 0eh usb address register 07h control register 2 0fh sof low register (read only) 15h reserved 1dh1fh sof high register (read only) 16h reserved 25h-27h reserved 17h reserved 2dh-2fh dma total count low register 35h dma total count high register 36h reserved 37h memory buffer 40h ? ffh table 3-20. endpoints 0?3 register addresses endpoint register set address (in hex) endpoint 0 ? a 00 - 04 endpoint 0 ? b 08 - 0c endpoint 1 ? a 10 - 14 endpoint 1 ? b 18 - 1c endpoint 2 ? a 20 - 24 endpoint 2 ? b 28 - 2c endpoint 3 ? a 30 - 34 endpoint 3 ? b 38 - 3c table 3-21. register address map endpoint register sets (for endpoint n starting at register position index=0 ) index endpoint n control index + 1 endpoint n base address index + 2 endpoint n base length index + 3 endpoint n packet status index + 4 endpoint n transfer count
sl811hs document 38-08008 rev. *b page 13 of 32 3.2.3 endpoint control registers 3.2.3.1 endpoint n control register [addre ss a = (ep# * 10h), b = (ep# * 10h)+8] each endpoint set has a control r egister defined as follows: 3.2.3.2 endpoint base address [address a = (ep# * 10h)+1, b = (ep# * 10h)+9]] pointer to memory buffer location for usb reads and writes. 3.2.3.3 endpoint base length [address a = (ep# * 10h)+2, b = (ep# * 10h)+a] the endpoint base length is the maximum packet size for in/out transfers with the host. essentia lly, this designates the larges t packet size that can be received by the sl811hs with an out tran sfer, or it designates the size of the data packet to be sent t o the host for in transfers. 3.2.3.4 endpoint packet status [address a = (ep# * 10h)+3, b = (ep# * 10h)+bh] the packet status contains information relative to the packet that has been received or transmitted. the register is defined as follows: table 3-22. endpoint control regist er [address ep0a/b:00h/08h, ep1a/b:10h/ 18h, ep2a/b:20h/28h, ep3a/b:30h/38h] 7 6 5 4 3 2 1 0 reserved sequence send stall iso next data set direction enable arm bit position bit name function 7reserved 6 sequence sequence bit. '0' if data0, '1' if data1. 5 send stall when set to ?1? sends stall in response to next request on this endpoint. 4 iso when set to '1' allows isochronous mode for this endpoint. 3 next data set '0' if next data set is ?a?, '1' if next data set is 'b'. 2 direction when direction = '1' transmit to host (i n). when direction = '0', receive from host (out). 1 enable when enable = '1' allows transfers for th is endpoint. when set 0 usb transactions are ignored. if enable = '1' and arm = '0', the en dpoint will return naks to usb transmissions. 0 arm allows enabled transfers when set =?1?. clears to '0' when transfer is complete. table 3-23. endpoint base addr ess reg [address; ep0a/b:01h/09h, ep1a/b:11h/19h, ep2a/b:21h /29h, ep3a/b:31h/39h] 7 6 5 4 3 2 1 0 epxadd7 epxadd6 epxadd5 epxadd4 epxadd3 epxadd2 epxadd1 epxadd0 table 3-24. endpoint base leng th reg [address ep0a/b:02h/0ah, ep1a/b:12h/1ah, ep2a/b:22h /2ah, ep3a/b:32h/3ah] 7 6 5 4 3 2 1 0 epxlen7 epxlen6 epxlen5 epxlen4 epxlen3 epxlen2 epxlen1 epxlen0 table 3-25. endpoint pack et status reg [address ep0a/b:03h/0bh, ep1 a/b:13h/1bh, ep2a/b:23h/2bh, ep3a/b:33h/3bh] 7 6 5 4 3 2 1 0 reserved reserved overflow setup sequence time-out error ack bit position bit name function 7reserved na 6reserved na 5 overflow overflow condition - maximum length exceeded during receives. this is considered a serious error. the maximum number of bytes t hat can be received by an endpoint is deter- mined by the endpoint base length register fo r each endpoint. the overflow bit is only relevant during out tokens from the host. 4 setup '1' indicates setup packet. if this bit is set, the last packet rece ived was a setup packet.
sl811hs document 38-08008 rev. *b page 14 of 32 3.2.3.5 endpoint transfer count [address a = (ep# * 10h)+4, b = (ep# * 10h)+ch] as a peripheral device, the endpoint transfer count register is only important with out tokens (host sending the slave data). when a host sends the peripheral data, the transfer count regist er will contain the difference between the endpoint base length and the actual number of bytes received in the last packet. in other words if the endpoint base length register was set for 64 (40h) bytes and an out token was sent to the endpoint that only had 16 (10h) bytes, th e endpoint transfer count register would have a value of 48 (30h). if more bytes were sent in an out token then the endpoint base len gth register was programmed for the overflow flag will be set in the endpoint packet st atus register and is considered a serious error. 3.2.4 usb control registers the usb control registers manage communication and data flow on the usb. each usb device is composed of a collection of independently operating endpoints. each endpoint has a unique i dentifier, which is the endpoint number. for more details about usb endpoints, please refer to the u sb specification 1.1, section 5.3.1. the control and status registers are mapped as follows: 3.2.4.1 control regist er 1, address [05h] the control register enables or disables usb tr ansfers and dma operations with control bits. 3 sequence the sequence bit indicates if the last packet was a data0 (0) or data1 (1). 2 time-out this bit is not used in slave mode. 1 error error detected in transmission, this includes crc5/16 and pid errors. 0 ack transmission acknowledge. table 3-26. endpoint transfer count reg [address ep0a/b:04h/0ch, ep1a/b:14h/1ch, ep2a/b:24h /2ch, ep3a/b:34h/3ch] 7 6 5 4 3 2 1 0 epxcnt7 epxcnt6 epxcnt5 epxcnt4 epxcnt3 epxcnt2 epxcnt1 epxcnt0 bit position bit name function table 3-27. control and status register map register name address (in hex) control register 1 05h interrupt enable register 06h usb address register 07h interrupt status register 0dh current data set register 0eh control register 2 0fh sof low byte register 15h sof high byte register 16h dma total count low byte register 35h dma total count high byte register 36h table 3-28. control register 1 [address 05h] 7 6 5 4 3 2 1 0 reserved stbyd spsel j-k1 j-k0 dma dir dma enable usb enable bit position bit name function 7 reserved reserved bit - must be set to '0'. 6 stbyd xcvr power control. 1 sets xcvr to low power. for normal operation set this bit = 0. suspend mode is entered if bit 6 = 1 and bit 0 (usb enable) = 0. 5 spsel speed select. 0 selects full-speed. 1 selects low-speed (also see ta ble 3 -3 4 )
sl811hs document 38-08008 rev. *b page 15 of 32 3.2.4.2 interrupt enable register, address [06h] the sl811hs provides an interrupt request ou tput that is activated resu lting from a number of conditions. the interrupt enable register allows the user to select events that will generate th e interrupt request output assertion. a separate interrupt statu s register can be read in order to determine the condition that initiated the interrupt (see interru pt status register descriptio n section 3.2.4.4 ). when a bit is set to 1, the corresponding interrupt is enabled. setting a bit in the interrupt enable register does not effect the interrupt status regi ster?s value, it just determines which interrupts will be output on intrq. 3.2.4.3 usb address register, address [07h] this register contains the usb device address after assignment by usb host during configuration. on power up or reset, usb address register is set to address 00h. after usb configuratio n and address assignment, the device will recognize only usb transactions directed to the address contained in the usb address register. 4 j-k1 j-k1 and j-k0 force state control bits can be used to generate various usb bus conditions. forcing k-state can be used for peripheral device remote wake-up, resume and other modes. these two bits are set to zero on power up see table 3-29 for functions. 3j-k0 2 dma dir dma transfer direction bit. set equal to 1 for dma read cycles from sl811hs, set equal to 0 for dma write cycles. 1 dma enable enable dma operation when equal to 1. disable = 0. dma is initiated when dma count high is written. 0 usb enable overall enable for transfers. 1 enables and 0 disables. this bit should be set to 1 to enable usb communication. default at power on = 0 bit position bit name function table 3-29. j-k force-state control bits jk-force state usb engine reset function 0 0 normal operating mode 0 1 force se0, d+ and d? are set low 1 0 force k-state, d? set high, d+ set low 1 1 force j-state, d+ set high, d? set low table 3-30. interrupt enable register [address: 06h] 7 6 5 4 3 2 1 0 dma status usb reset sof received dma done endpoint 3 done endpoint 2 done endpoint 1 done endpoint 0 done bit position bit name function 7 dma status when equal to 1, indicates dma transfer is in progress; when equal to 0, indicates dma transfer is complete. 6 usb reset enable usb reset received interrupt when = 1. 5 sof received enable sof received interrupt when = 1. 4 dma done enable dma done interrupt when = 1. 3 endpoint 3 done enable endpoint 3 done interrupt when = 1. 2 endpoint 2 done enable endpoint 2 done interrupt when = 1. 1 endpoint 1 done enable endpoint 1 done interrupt when = 1. 0 endpoint 0 done enable endpoint 0 done interrupt when = 1. table 3-31. usb address register [address 07h] 7 6 5 4 3 2 1 0 usbadd7 usbadd6 usbadd5 usbadd4 usbadd3 usbadd2 usbadd1 usbadd0
sl811hs document 38-08008 rev. *b page 16 of 32 3.2.4.4 interrupt status register, address [0dh] this read/write register serves as an interrupt status register when it is read, and an interrupt clear register when it is wri tten. to clear an interrupt, the register must be written with the appropriate bit set to 1. writing a 0 has no effect on the status. 3.2.4.5 current data set register, address [0eh] this register indicates currently selected data set for each endpoint. 3.2.4.6 control register 2, address [0fh] control register 2 is used to control if the device is configured as a master or a slave and can change the polarity of the dat a+ and data- pins to accommodate both full and low speed operation. table 3-32. interrupt stat us register [address 0dh] 7 6 5 4 3 2 1 0 dma status usb reset sof received dma done endpoint 3 done endpoint 2 done endpoint 1 done endpoint 0 done bit position bit name function 7 dma status when equal to 1, indicates dma transfer is in progress; when equal to 0, indicates dma transfer is complete. an interrupt is not generated when dma is complete. 6 usb reset usb reset received interrupt. 5 sof received sof received interrupt. 4 dma done dma done interrupt. 3 endpoint 3 done endpoint 3 done interrupt. 2 endpoint 2 done endpoint 2 done interrupt. 1 endpoint 1 done endpoint 1 done interrupt. 0 endpoint 0 done endpoint 0 done interrupt. table 3-33. current data set register [address 0eh] 7 6 5 4 3 2 1 0 reserved endpoint 3 endpoint 2 endpoint 1 endpoint 0 bit position bit name function 7-4 reserved na. 3 endpoint 3 done endpoint 3a = 0, endpoint 3b = 1. 2 endpoint 2 done endpoint 2a = 0, endpoint 2b = 1. 1 endpoint 1 done endpoint 1a = 0, endpoint 1b = 1. 0 endpoint 0 done endpoint 0a = 0, endpoint 0b = 1. table 3-34. control register 2 [address 0fh] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sl811hs master/slave selection sl811hs d+/d? data polarity swap reserved bit position bit name function 7sl811hs master/slave selection master = 1 slave = 0
sl811hs document 38-08008 rev. *b page 17 of 32 3.2.4.7 sof low register, address [15h] read only register contains the 7 low order bits of frame number in positions: bit 7:1. bit 0 is undefined. register is updated when a sof packet is rece ived. user should not write to this register. 3.2.4.8 sof high regi ster, address [16h] read only register contains the 4 low order bits of frame number in positions: bit 7:4. bits 3:0 are undefined, and should be masked when read by the user. this register is updated when a sof packet is received. the user should not write to this register. 3.2.4.9 dma total count low register, address [35h] the dma total count low register contains the low order 8- bits of dma count. dma total count is the total number of bytes to be transferred between a peripheral to the sl811hs. the count may sometimes require up to 16-bits, thus the count is represented in two registers: total count low, and total count high. ep3 is only suppor ted with dma operation. 3.2.4.10 dma total count hig h register, address [36h] the dma total count high register contains the high order 8-bits of dma count. when written, this register enables dma if the dma enable bit is set in the control register 1. the user should always write low count register first, followed by a write to high count register, even if high count is 00h. 6 sl811hs d+/d? data polarity swap ?1? = change pola rity (low-speed) ?0? = no change of polarity (full-speed) 5-0 reserved na bit position bit name function
sl811hs document 38-08008 rev. *b page 18 of 32 4.0 sl811hs and SL811HST-AC physical connections this part is offered in both a 28-pin plcc package (sl811hs) and a 48-pin tqfp package (SL811HST-AC). 4.1 sl811hs physical connections 4.1.1 sl811hs pin layout *see pin and signal description for pins 2 and 3 in host mode. 4.1.2 28-pin plcc mechanical dimensions 1 2 28 ndrq* ndack* nrd nwr d7 d6 d5 d4 gnd d3 d2 d1 d0 gnd intrq vdd1 nrst vdd2 gnd ncs data- data+ vdd1 clk/x1 x2 sl811hs 28 plcc a0 m/s 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 22 21 20 19 18 27 26 23 cm figure 4-1. sl811hs usb host/slave controller?pin layout
sl811hs document 38-08008 rev. *b page 19 of 32 4.1.3 sl811hs usb host/slave pin description the sl811hs package is a 28-pin plcc. the device requires 3.3 vdc. average typical current consumption is less then 20 ma for 3.3v. notes: 4. the a0 address bit is used to access address or data registers in i/o-mapped or memory-mapped applications. 5. the cm clock multiplier pin should be tied high for a 12-mhz cl ock source and tied to ground for a 48-mhz clock source. in sl 11h, this pin was designated as an ale input pin. 6. v dd can be derived from the usb supply. the diagram below shows a simple method to prov ide 3.3v/30 ma. another option is to use a torex semiconductor, ltd. 3.3v smd regulator (part number xc62hr3302mr). 7. the x1/x2 clock requires external 12- or 48-mhz matching crystal or clock source. table 4-1. sl811hs pin assignments and definitions pin no. pin type pin name pin description 1 in a0 a0 = ?0.? selects address pointer . reg. write only. selects data buffer or register. r/w. [4] 2 in ndack dma acknowledge . an active low input used to interface to an external dma controller. this works only in slave mode. in host mode, pin should be tied to logic ?1? in host mode. 3 out ndrq dma request . an active low output used with an external dma controller. ndrq and ndack form the handshake for dma data transfers. in host mode, pin must be left unconnected in host mode. 4 in nrd read strobe input . an active low input used with ncs to read registers/data memory. 5 in nwr write strobe input . an active low input used with ncs to write to registers/data memory. 6 in ncs active low chip select . used with nrd and nwd when accessing sl811hs. 7 in cm clock multiply . select internal 4 x clock multiplier. ?1? enables 4x clock multiplier. ?0? disables. [5] 8 vdd1 +3.3 vdc power for usb transceivers. 9 bidir data + usb differential data signal high side. 10 bidir data - usb differential data signal low side. 11 gnd usb gnd ground connection for usb. 12 vdd +3.3 vdc sl811hs device v dd power [6] 13 in clk/x1 12-/48-mhz clock or external crystal x1 connection [7] 14 out x2 external crystal x2 connection. 15 in nrst sl811hs device active low reset input. 16 out intrq active high interrupt request output to external controller. 17 gnd gnd sl811hs device ground. 18 bidir d0 data 0. microprocesso r data/(address) bus. 19 bidir d1 data 1. microprocesso r data/(address) bus. 20 bidir d2 data 2. microprocesso r data/(address) bus. 21 bidir d3 data 3. microprocesso r data/(address) bus. 22 gnd gnd sl811hs device ground. 23 bidir d4 data 4. microprocesso r data/(address) bus. 24 bidir d5 data 5. microprocesso r data/(address) bus. 25 bidir d6 data 6. microprocesso r data/(address) bus. 26 bidir d7 data 7. microprocesso r data/(address) bus. 27 in m/s master/slave select. ho st = ?0,? slave = ?1?. 28 vdd +3.3 vdc sl811hs device v dd power.
sl811hs document 38-08008 rev. *b page 20 of 32 the diagram below illustrates a simple +3.3v voltage source. 4.1.4 package markings (sl811hs) yyww = date code xxxx = product code x.x = silicon revision number +5 v ( u s b ) gnd r1 +3 . 3 v ( v d d ) sample vdd generator 45 ohms 3.9v, 1n52288ct- zener 2n2222 sl811hs yyww-x.x xxxx
sl811hs document 38-08008 rev. *b page 21 of 32 4.2 SL811HST-AC physical connections 4.2.1 SL811HST-AC pin layout *see pin and signal description for pins 43 and 44 in host mode. 4.2.2 mechanical dimensions 48-pin tqfp note: 8. nc. indicates no connection. nc pins should be left unconnected. sl811hst 1 12 13 24 25 48 37 36 nc nc nc nc nc nc nc nc nc nc data- nrd nc nc nc nc nc nwr ncs cm vdd1 data+ vdd clk/x1 x2 nrst intrq gnd d0 d1 d2 d3 gnd d4 d5 d6 d7 vdd m/s a0 ndack* nc [8] ndrq* usbgnd nc nc nc nc figure 4-2. SL811HST-AC usb ho st/slave controller pin layout
sl811hs document 38-08008 rev. *b page 22 of 32 4.2.3 SL811HST-AC usb host controller pins description the SL811HST-AC is packaged in a 48-pin tqfp. the device requires a 3.3vdc power source. the SL811HST-AC requires an external 12 or 48 mhz crystal or clock. table 4-2. SL811HST-AC pin assignments and definitions pin no. pin type pin name pin description 1 nc nc nc 2 nc nc nc 3 in nwr write strobe input . an active low input used with ncs to write to registers/data memory. 4 in ncs active low SL811HST-AC chip select . used with nrd and nwr when accessing sl811ht. 5 in cm clock multiply . select 12-mhz/48-mhz clock source. [9] 6 vdd1 +3.3 vdc power for usb transceivers . v dd1 may be connected to v dd . 7 bidir data + usb differential data signal high side. 8 bidir data - usb differential data signal low side. 9 gnd usb gnd ground connection for usb. 10 nc nc nc 11 nc nc nc 12 nc nc nc 13 nc nc nc 14 nc nc nc 15 vdd +3.3 vdc SL811HST-AC device v dd power. [10] 16 in clk/x1 clock or external crystal x1 connection. [11] 17 out x2 external crystal x2 connection. 18 in nrst SL811HST-AC device active low reset input. 19 out intrq active high interrupt request output to external controller. 20 gnd gnd SL811HST-AC device ground. 21 bidir d0 data 0 . microprocessor data/(address) bus. 22 nc nc nc 23 nc nc nc 24 nc nc nc 25 nc nc nc 26 nc nc nc 27 bidir d1 data 1 . microprocessor data/(address) bus. 28 bidir d2 data 2 . microprocessor data/(address) bus. 29 bidir d3 data 3 . microprocessor data/(address) bus. 30 gnd gnd SL811HST-AC device ground. 31 bidir d4 data 4 . microprocessor data/(address) bus. 32 bidir d5 data 5 . microprocessor data/(address) bus. notes: 9. the cm clock multiplier pin should be tied high for a 12-mhz clock source and tied to ground for a 48-mhz clock source. in sl 11h, this pin was designated as ale input pin. 10. vdd can be derived from the usb supply. see diagram. 11. the x1/x2 clock requires external 12- or 48-mhz matching crystal or clock source.
sl811hs document 38-08008 rev. *b page 23 of 32 notes: 12. the a0 address bit is used to access address register or data registers in i/o mapped or memory mapped applications. 4.2.4 package markings (SL811HST-AC) yyww = date code xxxx = product code x.x = silicon revision number 33 bidir d6 data 6 . microprocessor data/(address) bus. 34 nc nc nc 35 nc nc nc 36 nc nc nc 37 nc nc nc 38 nc nc nc 39 bidir d7 data 7 . microprocessor data/(address) bus. 40 in m/s master/slave mode select . ?1? selects slave. ?0? = master. 41 vdd +3.3 vdc SL811HST-AC device v dd power. 42 in a0 a0 = ?0.? selects address pointer. reg.a0 = ?1.? selects data buffer or register. [12] 43 in ndack dma acknowledge . an active low input used to interface to an external dma controller. dma is enabled only in slave mode. in host mode, pin should be tied high (logic ?1?). 44 out ndrq dma request . an active low output used with an external dma controller. ndrq and ndack form the handshake for dma data transfers. in host mode, pin must be left unconnected. 45 in nrd read strobe input . an active low input us ed with ncs to read registers/data memory. 46 nc nc nc 47 nc nc nc 48 nc nc nc table 4-2. SL811HST-AC pin assignments and definitions (continued) pin no. pin type pin name pin description sl811hst yyww-x.x xxxx
sl811hs document 38-08008 rev. *b page 24 of 32 5.0 electrical specifications 5.1 absolute maximum ratings this section lists the absolute maximum ratings of the sl81 1hs. stresses above those listed can cause permanent damage to the device. exposure to maximum rated conditions for ext ended periods can affect device operation and reliability. 5.2 recommended operating condition 5.3 external clock input characteristics (x1) notes: 13. the sl811hs can use a 12-mhz crystal oscillator or 12-mhz clock source. 14. fundamental mode for 12-mhz crystal. 15. the sl811hs can use a 12-mhz clock source. storage temperature ?40c to 125c voltage on any pin with respect to ground ?0.3v to 6.0v power supply voltage (v dd ) 4.0v power supply voltage (v dd1 ) 4.0v lead temperature (10 seconds) 180c parameter min. typical max. power supply voltage, vdd 3.0v 3.3v 3.45v power supply voltage, vdd1 3.0v 3.45v operating temperature 0c 65c crystal requirements, (x1, x2) min. typical max. operating temperature range 0c 65c parallel resonant frequency [13] 48 mhz frequency drift over temperature 50 ppm accuracy of adjustment 30 ppm series resistance 100 ohms shunt capacitance 3 pf 6 pf load capacitance 20 pf drive level 20 w 5 mw mode of vibration third overtone [14] parameter min. typical max. clock input voltage @ x1 (x2 open) 1.5 v clock frequency [15] 48 mhz
sl811hs document 38-08008 rev. *b page 25 of 32 5.4 dc characteristics 5.5 usb host transceiver characteristics every v dd pin, including usb v dd , has to have a decoupling capacitor to ensure clean v dd (free of high-frequency noise) at the chip input point (pin) itself. the best way to do this is to connect a ceramic capacitor (0.1 f, 6v) between the pin itself and a good ground. capacitor leads must be kept as short as possible. use surface mount capacitors with the shortest traces possib le (the use of a ground plane is strongly recommended). parameter description min. typ. max. v il input voltage low ?0.3 v 0.8v v ih input voltage high (5v tolerant i/o) 2.0 v 6.0v v ol output voltage low (i ol = 4 ma) 0.4v v oh output voltage high (i oh = ?4 ma) 2.4 v i oh output current high 4 ma i ol output current low 4 ma i ll input leakage 1 a c in input capacitance 10 pf i cc [16] supply current (v dd ) inc usb @fs 21 ma 25 ma i ccsus1 [17] supply current (v dd ) suspend w/clk & pll enb 4.2 ma 5 ma i ccsus2 [18] supply current (v dd ) suspend no clk & pll dis 50 a 60 a i usb supply current (v dd1 ) 10 ma i usbsus transceiver supply current in suspend 10 a parameter description min. typ. [19] max. v ihys differential input sensitivity (data+, data?) 0.2v 200 mv v usbih usb input voltage high driven 2.0 v usbil usb input voltage low 0.8v v usboh usb output voltage high 2.0v v usbol usb output voltage low 0.0v 0.3 v z usbh [20] output impedance high state 36 ohms 42 ohms z usbl [20] output impedance low state 36 ohms 42 ohms i usb transceiver supply p-p current (3.3v) 10 ma @ fs notes: 16. i cc measurement includes usb transceiver current (i usb ) operating at full speed. 17. i ccsus1 measured with 12-mhz clock input and internal pll enabled. su spend set ?(usb transceiver and internal clocking disabled). 18. i ccsus2 measured with external clock, pll disabled, and suspend set. for absolute minimum current consumption, ensure that all inputs to the device are at static logic level. 19. all typical values are v dd = 3.3v and t amb = 25c. 20. z usbx impedance values includes an external resistor of 24 ohms 1% (sl811hs revision 1.2 requires external resistor values of 33 o hms 1%).
sl811hs document 38-08008 rev. *b page 26 of 32 5.6 bus interface timing requirements 5.6.1 i/o write cycle note: ncs an be held low for multiple write cycles provided nwr is cycled. write cycle time for auto inc mode writes is 170 ns minimum. parameter description min. typ. max. t wr write pulse width 85 ns t wcsu chip select set-up to nwr low 0 ns t wshld chip select hold time after nwr high 0 ns t wasu a0 address set-up time 85 ns t wahld a0 address hold time 10 ns t wdsu data to write high set-up time 85 ns t wdhld data hold time after write high 5 ns t cscs ncs inactive to ncs* asserted 85 ns t wrhigh nwr high 85 ns nwr a0 d0-d7 data twr twahld twdhld twasu twdsu twdsu twdhld i/o write cycle to register or memory buffer register or memory a ddress ncs twcsu twshld tcscs see note. twrhigh
sl811hs document 38-08008 rev. *b page 27 of 32 5.6.2 i/o read cycle note . ncs can be kept low during mu ltiple read cycles provided nrd is cycled. rd cycle time for au to inc mode reads is 170 ns minimum. nrd a0 d0-d7 data twr twahld twdhld twasu twdsu trdhld i/o read cycle from register or memory buffer register or memory a ddress trdp nwr trshld trcsu ncs tracc tcscs *note twrrdl parameter description min. typ. max. t wr write pulse width 85 ns t rd read pulse width 85 ns t wcsu chip select set-up to nwr 0 ns t wasu a0 address set-up time 85 ns t wahld a0 address hold time 10 ns t wdsu data to write high set-up time 85 ns t wdhld data hold time after write high 5 ns t racc data valid after read low 25 ns 85 ns t rdhld data hold after read high 40 ns t rcsu chip select low to read low 0 ns t rshld ncs hold after read high 0 ns t cscs * ncs inactive to ncs *asserted 85 ns t wrrdl nwr high to nrd low 85ns
sl811hs document 38-08008 rev. *b page 28 of 32 5.6.3 dma write cycle note: n wr must go low after n dack goes low in order for n drq to clear. if this sequence is not implemented as requested, the next n drq will be not inserted. parameter descrip tion min. typ. max. tdack ndack low 80 ns tdwrlo ndack to nwr low delay 5 ns tdakrq ndack low to ndrq high delay 5 ns tdwrp nwr pulse width 65 ns tdhld data hold after nwr high 5 ns tdsu data set-up to nwr strobe low 60 ns tackrq ndack high to ndrq low 5 ns tackwrh ndack high to ndrq low 5 ns twrcycle dma write cycle time 150 ns ndrq ndack d0-d7 data nwr tdwrp tdsu tdack tdhld tdwrlo tackwrh tdakrq tackrq
sl811hs document 38-08008 rev. *b page 29 of 32 5.6.4 dma read cycle note: data is held until ndack goes high regardless of state of nread. 5.6.5 reset timing note . clock is 48-mhz nominal. parameter description min. typ. max. tdack ndack low 100 ns tddrdlo ndack to nrd low delay 0 ns tdckdr ndack low to ndrq high delay 5 ns tdrdp nrd pulse width 90 ns tdhld [] date hold after ndack high 5 ns tddaccs data access from ndack low 85 ns tdrdack nrd high to ndack high 0 ns tdakrq ndrq low after ndack high 5 ns trdcycle dma read cycle time 150 ns ndrq ndack d0-d7 data nrd sl811 dma read cycle timing tdrdp tdaccs tdack tdhld tddrdlo tdckdr tdakrq nrst nrd or nwr treset tioact reset timing parameter description min. typ. max. t reset nrst pulse width 16 clocks t ioact nrst high to nrd or nwr active 16 clocks
sl811hs document 38-08008 rev. *b page 30 of 32 5.6.6 clock timing specifications 6.0 package diagrams clk clock timing trise tfall thigh tclk tlow parameter description min. typ. max. t clk clock period (48 mhz) 20.0 ns 20.8 ns t high clock high time 9 ns 11 ns t low clock low time 9 ns 11 ns t rise clock rise time 5.0 ns t fall clock fall time 5.0 ns clock duty cycle 45% 55% dimensions in inches min. max. 0.045 0.055 0.026 0.013 0.032 0.021 0.020 min. 0.090 0.165 0.120 0.180 0.485 0.495 0.450 0.458 0.458 0.450 0.495 0.485 0.390 0.430 426 18 12 11 5 19 25 0.004 seating plane 1 pin #1 id 28-lead plastic leaded chip carrier j64 51-85001-*a
sl811hs document 38-08008 rev. *b page 31 of 32 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. intel is a registered trademark of intel corporation. torex is a trademark of torex semiconductors, ltd. sl811hs is a trademark of cypress semiconductor cor poration. all product and company names mentioned in this document may be the trademarks of their respective holders. 48-lead thin plastic quad flat pack (7x7x1.4 mm) a48 51-85135-**
sl811hs document 38-08008 rev. *b page 32 of 32 document history page document title: sl811hs usb host/sl ave controllers hardware specification document number: 38-08008 rev. ecn no. issue date orig. of change description of change ** 110850 12/14/01 bha converted to cypress format from scanlogic *a 112687 03/22/02 mul 1) changed power supply voltage to 4.0v in section 7.1 2) changed value of twdsu in section 7.6.2 3) changed max. power supply voltage to 3.45 v in section 7.2 4) changed accuracy of adjustment in section 7.2 5) changed bits 0 and 1 to reserved in section 5.3.8 6) changed bit 2 to reserved in section 5.3.5 and 5.3.7 7) changed bit 2 to reserved in section 5.3.1 8) changed definition of bit 6 in section 5.3.5 & 5.3.7 9) added section 5.1, register values on power-up and reset 10) changed bit description notes in section 5.3.7 11) changed note about series termi nation resistors in section 7.5 12) changed example in section 5.3.9 13) changed j-k programming states table in section 5.3.2 14) added and removed comments for low-power modes in section 5.3.4 15) removed sections specific to slave operation and sl11h 16) removed duplicate tables 17) general formatting changes to section headings 18) fixed all part number references 19) added comments to section 7.5 and new definitions to section 2.0 *b 381894 see ecn vcs went from single column to 2-column format. combined information from sl811hs (38-08008) and sl811s/t (83-08009).

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